`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/02/11 11:49:53
// Design Name: 
// Module Name: led
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module led(
input CLK,output reg[3:0] led_out
    );
    reg [32:0] count=0;
    reg p=1;
    always @ (posedge CLK)
    begin
     if(count < 50000000)
     begin
       if(p == 1)
        begin
         led_out <=  4'b0001;
         p <=0 ;
       end
       count <= count + 1;
     end
     else
     begin
      if(led_out == 4'b1000)
      begin
          led_out <= 4'b0001;
      end
      else
         led_out <= led_out << 1;
       count <= 0;    
     end
    end
endmodule
